Faculty of Electronic Engineering, Niš, Serbia

Faculty of Electronic Engineering, Niš, Serbia

The paper is available at the following link: PDF

Abstract:

This paper presents design, implementation, and comparative analysis of three circuits computing the square root of fixed-point numbers. The circuits are first described in VHDL and then, they are synthesized and implemented using Cadence tools - Genus and Innovus, in technology node TSMC 65nm. The design process starts with RTL description and ends with ASIC layout design. Performance of each circuit is evaluated across three critical metrics: computational latency, dynamic, static power consumption and occupied area. Our results reveal trade- offs between these metrics, required by different applications. The design process provides practical insights for selecting square root implementations in area-constrained and power-sensitive applications.

Keywords:

Square root algorithms, ASIC, TSMC 65nm, Cadence.

REFERENCES:

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